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-- Company: 

-- Engineer: 

-- 

-- Create Date: 2025/03/17 16:08:25

-- Design Name: 

-- Module Name: ex101 - Behavioral

-- Project Name: 

-- Target Devices: 

-- Tool Versions: 

-- Description: 

-- 

-- Dependencies: 

-- 

-- Revision:

-- Revision 0.01 - File Created

-- Additional Comments:

-- 

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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx leaf cells in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity ex101 is

    Port ( in0 : in STD_LOGIC;

           out0 : out STD_LOGIC);

end ex101;

architecture Behavioral of ex101 is

begin

    OUT0 <= INO ; --  INO 의 값을 OUT 에 대입한다. 

end Behavioral;